Invalidating cache line
Based on the invalided state of the cache reset address line, the processor obtains new instructions from data memory.The new instructions can be configured to invalidate the remaining cache lines using software mechanisms. Field of the Invention The present invention relates to processors.In one example, the present invention relates to methods and apparatus for processors handling and event such as a fault or reset event. Description of Related Art Conventional computer systems have processors coupled to system memory.In order to optimize access to data in system memory, individual processors are typically designed to work with cache memory.
Any event such as a fault or manual reset is referred to herein as a reset event.
A processor cache line may be shared, modified, exclusive, owned, or invalid.
In some instances, a processor may only be able to distinguish between valid and invalid cache lines.
An instruction cache includes operation codes (opcodes) and parameters identifying the operations a processor should perform.
Data cache typically includes data values associated with the operations.